Low-k dielectrics are those having a smaller dielectric constant than silicon dioxide (SiO2). Silicon dioxide has a dielectric constant of 3.9. Low-k dielectric materials are positioned between conducting elements in integrated circuits to improve achievable switching speed and reduce power consumption as feature sizes are decreased. Low-k dielectric films are achieved by selecting film materials which reduce dielectric constant and/or inserting pores inside the film.
Besides decreasing the dielectric constant, the conductivity of the conducting elements (e.g. metal lines) can be increased. As a consequence, copper has replaced many other metals for longer lines (interconnects). Copper has a lower resistivity and higher current carrying capacity. However, precautions must be taken to discourage diffusion of copper into surrounding materials. Besides the need to inhibit diffusion into active semiconductor areas, copper should be kept from entering porous low-k dielectric regions to avoid shorting and maintain the low dielectric constant.
An example of an integrated circuit structure which implements copper as an interconnect material is a dual-damascene structure. In a dual-damascene structure, the dielectric layer is etched to define both the contacts/vias and the interconnect lines. Metal is inlaid into the defined pattern and any excess metal is removed from the top of the structure in a planarization process, such as chemical mechanical polishing (CMP).
Novel liner layers and/or process modifications are needed to achieve high conductivity for the interconnect connections in combination with a low-k for the dielectric material.